1. Field of the Invention
The present invention relates generally to input buffer circuits for semiconductor integrated circuit devices, and more particularly, to an input buffer circuit which comprises a level shift circuit using a bipolar transistor. The present invention has particular applicability to address input buffer circuits in a BiCMOS RAM.
2. Description of the Background Art
Generally, a circuit comprising bipolar transistors takes a large current, but it can achieve high speed operation and large load driving capability. The circuit comprising a CMOS transistor cannot operate as fast as the bipolar transistor circuit, but it can operate under less current consumption, and a high integration density level can be attained. Accordingly, a BiCMOS integrated circuit device comprises the bipolar transistor and the CMOS transistor formed on a single semiconductor substrate to make full use of the advantage of the bipolar transistor circuit and the CMOS transistor circuit.
The BiCMOS integrated circuit device receives an externally applied input signal having an amplitude following an emitter coupled logic (referred to as "ECL" hereinafter) and comprises an input circuit for driving the internal CMOS transistor circuit. In the following description, a BiCMOS RAM will be described as one example of the BiCMOS integrated circuit device to which the present invention can be preferably applied. For example, the BiCMOS RAM is often use in a secondary cache memory of a general purpose large computer, a main memory of a super computer, and a cache memory of an engineering work station (EWS) order to utilize, for example, the advantage of high speed operation.
FIG. 5 is a block diagram of a BiCMOS RAM known in general. Referring to FIG. 5, the BiCMOS RAM 70 comprises a memory cell array 79 including a number of memory cells constructed by MOS transistors. A row address buffer 71 receives row address signals RAO to RAm having an ECL logic amplitude to drive a row decoder 72 comprising MOS transistors. Similarly, a column address buffer 73 receives column address signals CAO to CAn having the ECL logic amplitude to drive a column decoder 74 comprising MOS transistors. A sense amplifier 75 amplifies a data signal read out from the memory cell array 79. The BiCMOS RAM 70 further comprises a read/write control circuit 77 for receiving input data Din, a chip selecting signal/CS, and a write enable signal/WE and for controlling read/write operation, an output buffer 76 for providing read out data Do, and a V.sub.BB generator 78 generating a reference potential V.sub.BB. It should be noted that the row address buffer 71 and the column address buffer 73 drive the row decoder 72 and the column decoder 74 comprising MOS transistors in response to the externally applied address signal having the ECL logic amplitude. In other words, it should be noted that the row address buffer 71 and the column address buffer 73 convert the input signal having the externally applied ECL logic amplitude to the signal having the MOS logic amplitude.
FIG. 6 is a circuit diagram of a conventional input buffer circuit. The input buffer circuit is applicable in a row address buffer 71 or in a column address buffer 73 shown in FIG. 5. Referring to FIG. 6, the input buffer circuit comprises a first step level shift circuit 50 receiving an input signal Vin, a differential amplifier circuit 51, a level shift circuit 52, current mirror circuits 53 and 54 for level conversion, and driver circuits 55 and 56. An npn transistor 1 has base connected to receive the input signal Vin having an ECL logic amplitude. The transistor 1 has the collector connected to ground potential Vcc and the emitter connected to a negative power supply potential V.sub.EE through a constant current source 2. In the ECL logic, the input signal Vin has -0.9 V at a "H" level and has -1.7 V at a "L" level. Generally, the negative power supply potential V.sub.EE is set to -4.5 V or -5.2 V.
The differential amplifier circuit 51 comprises npn transistors 6 and 9, resistors 5 and 8, and a constant current source 7. The transistor 6 has the collector connected to ground potential Vcc through the resistor 5. The transistor 9 has the collector connected to ground potential Vcc through the resistor 8. The emitters of the transistors 6 and 9 are connected together to the constant current source 7. The transistor 6 has the base connected to receive the input signal level shifted by the first step level shift circuit 50. The transistor 9 has the base connected to receive the reference potential V.sub.BB. The reference potential V.sub.BB is generated from the V.sub.BB generator 78 shown in FIG. 5. The reference potential V.sub.BB is set to an intermediate value between a low level and a high level of the signal applied to the base of the transistor 6.
The level shift circuit 52 comprises an npn transistor 12 nd a constant current source 79, and an npn transistor 15 and a constant current source 81, each connected in series between ground potential Vcc and the power supply potential V.sub.EE. Transistors 12 and 15 have their bases connected respectively to receive the output signal provided from the differential amplifier circuit 51. Level shifted signals /Va and Va are provided through the emitters of transistors 12 and 15, respectively.
Current mirror circuits 53 and 54 convert applied signals Va and /Va having the ECL logic amplitude to the signals Vb and /Vb having the CMOS logic amplitude, respectively. The current mirror circuit 53 comprises PMOS transistors 18 and 20, and NMOS transistors 19 and 21. Transistors 18 and 19 are connected in series between ground potential Vcc and the power supply potential V.sub.EE. Transistors 20 and 21 are connected in series between ground potential Vcc and the power supply potential V.sub.EE. Transistors 19 and 21 have their gates connected together to a common connection node of the transistors 18 and 19. The transistor 18 has the gate connected to receive the level shifted signal /Va. The transistor 20 has the gate connected to receive the level shifted signal Va. The current mirror circuit 54 comprises PMOS transistors 22 and 24, and NMOS transistors 23 and 25, and it has the same circuit construction as the current mirror circuit 53. The current mirror circuit 53 provides the level converted signal /Vb through the common connection node of the transistors 20 and 21. Similarly, the current mirror circuit 54 provides the level converted signal Vb through the common connection node of the transistors 24 and 25.
The driver circuit 55 comprises npn transistors 30 and 31 connected in series between ground potential Vcc and the power supply potential V.sub.EE, a PMOS transistor 26 and an NMOS transistor 27 constituting an inverter for controlling the base of the transistor 30, and NMOS transistors 28 and 29 for controlling the base of the transistor 31. The gate of each of the transistors 26, 27, and 28 receives the signal /Vb. Through the common connection node of the emitter of the transistor 30 and the collector of the transistor 31, the output signal Vo is provided to drive the next stage MOS transistor circuit, not shown. The driver circuit 56 has the same circuit construction as the driver circuit 55. That is, the driver circuit 56 comprises npn transistors 36 and 37, a PMOS transistor 32 and an NMOS transistor 33 for controlling the base of the transistor 36, and NMOS transistors 34 and 35 for controlling the base of the transistor 37. The gate of each of the transistors 32, 33, and 34 receives the level shifted signal Vb. Through the common connection node of the transistors 36 and 37, the signal /Vo is provided to drive the circuit connected to next stage.
The operation will be described. When the input signal Vin having the ECL logic amplitude turns from a low level to a high level, the base potential of the transistor 6 also turns from a low level to a high level. Then, the transistor 6 turns on, while the transistor 9 turns off. By the turning on of the transistor 6, the base potential of the transistor 12 attains a low level determined by (Vcc-R.sub.5 .multidot.I.sub.7), where, R.sub.5 represents resistance value of the resistor 5, and I.sub.7 represents current value of the constant current source 7. In addition, by the turning off of the transistor 9, the base potential of the transistor 15 attains a high level almost as high as ground potential Vcc. Accordingly, the signal /Va representing the emitter potential of the transistor 12 attains a low level determined by the potential (Vcc-R.sub.5 .multidot.I.sub.7 -V.sub.BE12). The signal Va representing the emitter potential of the transistor 15 attains a high level determined by (Vcc-V.sub.BE15), where, V.sub.BE12 and V.sub.BE15 represent the base to emitter voltage of transistors 12 and 15.
In the current mirror circuits 53 and 54, transistors 18 and 24 turn on in response to a low level signal /Va, and transistors 20 and 22 turn off in response to a high level signal Va. Therefore, the output signal /Vb of the current mirror circuit 53 turns from a high level (Vcc) to a low level (V.sub.EE), and the output signal Vb of the current mirror circuit 54 turns from a low level (V.sub.EE) to a high level (Vcc). These output signals Vb and /Vb have the CMOS logic amplitude. In other words, signals Va and /Va are converted to signals Vb and /Vb having the CMOS logic amplitude in response to the input signal Vin having the ECL logic amplitude.
Current mirror circuits 53 and 54 do not have large load driving capability since they are formed of CMOS transistors. For the purpose of increasing load driving capability, BiCMOS driver circuits 55 and 56 are provided for amplifying the current. When the signal Vb changes from a high level (Vcc) to a low level (V.sub.EE), the transistor 26 turns on, and transistors 27 and 28 turn off. Accordingly, since the transistor 29 turns on, npn transistors 30 and 31 turn on and off, respectively. As a result, a high level output signal Vo is provided. At the same time, since the signal Vb changes from a low level to a high level, the transistor 32 turns off, and transistors 33 and 34 turn on. Accordingly, the transistor 35 turns off, and npn transistors 36 and 37 turn on and off, respectively. As a result, a low level output signal /Vo is provided.
When the input signal Vin having the ECL logic amplitude changes from a high level to a low level, the transistor 6 turns off, and the transistor 9 turns on. The base potential of the transistor 12 attains a high level almost as high as ground potential Vcc, and the base potential of the transistor 15 attains a low level determined by (V.sub.cc -R.sub.8 .multidot.I.sub.7). Accordingly, the signal/Va attains a high level determined by (Vcc-V.sub.BE12), and the signal Va attains a low level determined by (Vcc-R.sub.8 .multidot.I.sub.7 -V.sub.BE15), where, R.sub.8 represents resistance value of the resistor 8. Current mirror circuits 53 and 54, and driver circuits 55 and 56 receive signals Va and /Va, and operate in the same manner as the foregoing. Therefore, the description of the operation is not repeated.
FIG. 7 is a circuit diagram showing another example of a conventional input buffer circuit. The input buffer circuit is disclosed in an article "An 8 ns 256K BiCMOS RAM" (1988 IEEE International Solid-State Circuits Conference, Digest of Technical Papers pp. 184-185). When compared with the circuit shown in FIG. 6, the input buffer circuit shown in FIG. 7 comprises NMOS transistors 90 and 92 as controllable current sources in place of constant current sources 79 and 81. Namely, an improved level shift circuit 57 comprises the npn transistor 12 and the NMOS transistor 90, and the npn transistor 15 and the NMOS transistor 92, each serially connected between ground potential Vcc and the power supply potential V.sub.EE. The gate of the transistor 90 and the base of the transistor 15 are connected together to the collector of the transistor 9. The gate of the transistor 92 and the base of the transistor 12 are connected together to the collector of the transistor 6. Because other circuit construction of the input buffer circuit shown in FIG. 7 are similar to the one shown in FIG. 6, the description is not repeated. Furthermore, since the input buffer circuit shown in FIG. 7 operates basically in the same manner with the one shown in FIG. 6, the description is not repeated.
The problem in the input buffer circuit shown in FIG. 6 will be described. Since constant current sources 79 and 81 are connected to emitter of each of the transistors 12 and 15 constituting emitter followers, a certain constant current always flows through constant current sources 79 and 81. This implies that the current consumption is increased. In addition, since the level shift circuit 52 comprises emitter follower of transistors 12 and 15, output signals /Va and Va are decreased by the voltage V.sub.BE12 and V.sub.BE15. PMOS transistors 18, 20, 22, and 24 within current mirror circuits 53 and 54 operate in response to decreased signals/Va and Va. That is, PMOS transistors 18, 20, 22 and 24 are brought slightly to an on state because they receive signals/Va and Va decreased by the voltage V.sub.BE. Thus, a current flows between ground potential Vcc and the power supply potential V.sub.EE, and current consumption is further increased.
For the purpose of decreasing power consumption of the current flowing through constant current sources 79 and 81 shown in FIG. 6, NMOS transistors 90 and 92 shown in FIG. 7 work effectively. For example, when the input signal Vin changes from a low level to a high level, a collector potential of the transistor 6 turns from a high level to a low level. Since the gate of the NMOS transistor 92 as a current source is brought to a low level, the penetrating current flowing through the transistor 92 is decreased. Even when the input signal Vin changes from a high level to a low level, the penetrating current flowing through the transistor 90 is decreased because the gate of the transistor is brought to a low level. As a result, it becomes possible to decrease undesirable power consumption by constant current sources 79 and 81 shown in FIG. 6.
The input buffer circuit shown in FIG. 7 contributes to the decrease of power consumption as mentioned above: however, a new problem described hereinafter is caused. That is, transistors 90 and 92 shown in FIG. 7 have their gates connected to the base of npn transistors 15 and 12, respectively. In other words, the gate capacitances of transistors 90 and 92 are added to the gate of transistors 15 and 12, respectively. As a result, rise time and fall time of output signals Va and /Va provided from the level shift circuit 57 is increased. Transistors 90 and 92 prevent the level shift circuit 57 from achieving high speed operation. Even in the input buffer circuit shown in FIG. 7, it is pointed out that the increase of the power consumption cannot be prevented when the voltage V.sub.BE of signals Va and /Va is decreased.
FIG. 8 is a waveform diagram of the transition state of signals Va and /Va shown in FIG. 7. When an input signal Vin changes from a low level to a high level, two output signals Va and /Va of a level shift circuit 57 change in the way as shown in a dotted line in FIG. 8. Namely, since the gate capacitances of transistors 92 and 90 is added to the base of the npn transistors 12 and 15, respectively, undesirable time is required for signals Va and /Va to rise or fall. Furthermore, it is clear that the potential of the risen output signal Va attains the level lower than ground potential Vcc by the base to emitter voltage V.sub.BE.